Power-Saving Transmitter Delivers Faster Wireless Speeds for Next-Gen Devices

Innovative techniques eliminate the need for power-hungry CORDIC circuits, while ensuring linear modulation for future IoT and AI applications worldwide.

• Newly developed transmitter design bypasses conventional CORDIC, reducing power consumption
• Simultaneous gains in efficiency and data rates demonstrated in 65 nm CMOS
• Potentially supports growing demand for wireless IoT connectivity in modern AI-driven devices

Researchers in Japan have unveiled a novel transmitter design that aims to address two major bottlenecks in wireless communications: power efficiency and data throughput. The project builds on the increasing demand for rapid and reliable data transmission in an era shaped by artificial intelligence (AI) and the Internet of Things (IoT). The team at Science Tokyo has proposed three “innovative design techniques” that, according to their published findings, could open new possibilities for integrating advanced wireless transmitters into a range of electronic devices. The UK’s research community, frequently looking to extend battery life and bolster data rates for emerging scientific instruments, is one of many audiences who stand to benefit from improved efficiency in transmitter architectures.

Bypassing Power-Hungry Circuitry

“Three innovative design techniques substantially enhance wireless transmitter performance and can boost power efficiency and elevate data rates concurrently, as reported by the researchers from Science Tokyo, Japan.” This direct statement from the research team highlights their departure from traditional approaches that struggle to balance power consumption and data throughput. In most transmitters, converting Cartesian data into polar coordinates requires a circuit known as the COordinate Rotation DIgital Computer (CORDIC). This module is known to draw significant power, making it an obstacle for battery-dependent IoT devices that rely on low-energy operation.

By discarding the CORDIC block altogether, the researchers instead introduced Delta-Sigma Modulators (DSMs) to encode amplitude and phase information. Professor Kenichi Okada, who led the team at the Institute of Science Tokyo, explains, “The first proposed technique employs Delta-Sigma Modulators (DSMs) to re-encode the input data. Instead of directly calculating the polar coordinates of the input x and y signals, two DSMs convert them into 3-level signals. Because these 3-level outputs yield only nine distinct amplitude-phase combinations, a simple nine-state look-up table (LUT) can effectively determine the amplitude and phase.”

Unlike multi-bit modulators that demand complex correction and calibration, the use of 3-level signals minimises linearity errors. This streamlined design mitigates power loss and allows the transmitter to remain efficient, particularly significant for devices such as sensors and portable instruments that rely on limited power supplies.

Enhancing Modulation Accuracy

The second and third techniques were introduced to boost linearity without the need for power-intensive calibration, a factor that traditionally hampers transmitters as data rates increase. Reducing a 2-bit amplitude signal to 1-bit eliminates intermediate voltage states, ensuring the transmitted wave only toggles between zero and peak amplitude. This straightforward approach sidesteps non-idealities caused by mismatches in the fabrication process—an issue that can substantially distort signals in multi-bit systems.

For phase modulation, the research team employed a 3-bit control code and generated eight discrete phases, each separated by 45°. Rather than interpolating these phases continuously, they exploited the rising and falling edges of a square wave to produce the required shifts. This method similarly bypasses intricate circuitry and potential accuracy losses. The entire design was implemented on a 65 nm CMOS process for testing, demonstrating power efficiency and high data rates that compete with—or exceed—many existing transmitters.

Summarising the impact of their work, Okada states, “By applying these techniques, we achieved top-tier power efficiency and data rates among conventional transmitters, without compromising one for the other, thanks to our CORDIC-less polar transmitter architecture.” Such versatility may prove especially useful in the next generation of wireless devices, where battery life and high-speed connectivity are increasingly regarded as complementary, rather than competing, performance metrics.

This fresh approach, which uses established CMOS processes, could appeal to industrial and academic researchers alike, offering a feasible route to integrate advanced transmitters within mobile, wearable, and scientific instruments. As AI becomes ever more integrated into daily life—and the IoT ecosystem expands—the demand for simultaneously efficient and fast data links is set to grow, suggesting that these design techniques could find traction among both commercial developers.